1. Field of the Invention
The present invention relates to the field of fabricating semiconductor devices including field effect transistors (FETs), such as NMOS transistor elements and PMOS transistor elements, and, more particularly, to a method and a system for the improved controlling of the manufacturing process of field effect transistors to more reliably stabilize an electrical property of the completed devices.
2. Description of the Related Art
The dimensions of modem integrated circuits are steadily shrinking, while at the same time providing both improved device performance and circuit density. Both advantages are mainly obtained by steadily shrinking the feature sizes of the individual field effect transistor elements, such as MOS transistors, whereby critical dimensions, i.e., minimum feature sizes that can be reproducibly printed onto the substrate, are currently approaching the 0.1 xcexcm range, and further reductions are anticipated in the future. The formation of modem ultra-high density integrated circuits requires approximately 500 individual process steps, wherein one of the most critical steps is the formation of the gate electrode of the field effect transistors. The gate electrode controls, upon application of a suitable control voltage such as 2-3 volts or even less in modem CPUs, the current flow through a channel that forms below a thin gate insulation layer separating the gate electrode from the underlying semiconductor region. Generally, the gate electrode is designed to have a width dimension on the order of micrometers and a length dimension, also referred to as gate length, currently on the order of 0.1 micrometers. This gate length, which separates the highly doped source and drain regions of the field effect transistor, significantly affects the device performance with respect to signal propagation time and current flow from the source to the drain. Trimming the gate length down to a size of about 0.1 xcexcm necessitates an enormous effort to establish an appropriate lithography technique and a sophisticated etch trim method, wherein any deviation from a setting value of the gate length significantly contributes to a variation of the electrical properties of the completed transistor element. In particular, the on-current and the off-current, i.e., the current that flows when a conductive channel is formed between the source and the drain region and the current that flows when the conductive channel is not formed, as well as the switching speed, are greatly influenced by the gate length.
Generally, a reduced gate length leads to an increased on-current and to an increased switching speed of the transistor element. At the same time, however, the off-current, i.e., the undesired leakage current, also increases with a smaller gate length owing to an increased electrical field in the vicinity of the gate electrode. Accordingly, a reduced gate length compared to the setting value, although improving speed of the transistor element, may result in a lower yield of the completed transistor elements due to the increased and thus intolerable leakage current. On the other hand, an increased gate length compared to the setting value enhances the transistor characteristics with respect to leakage current, but entails a lower on-current and a lower speed of the transistor. As a consequence, circuit designers have to take into account the variation of the electrical properties of the individual transistor elements. Otherwise, the range of allowable gate lengths has to be set very tightly, thereby significantly reducing production yield and thus considerably contributing to the overall production costs.
In view of the above problems, it would be highly desirable to be able to control the electrical properties, such as the on-current and the off-current, the switching speed and the like, during the fabrication of the field effect transistors to improve yield and reproducibility of the devices.
Generally, the present invention is directed to a method and a system for controlling the process flow parameters for a field effect transistor on a run-to-run basis by at least partially compensating for the variation of the gate length by one or more of those process parameters of a subsequent process that tends to offset the effect of gate length variations on an electrical property under consideration.
According to one embodiment of the present invention, a method of controlling an electrical property of a field effect transistor during manufacturing the same comprises providing a substrate having formed thereon a gate electrode defining a length direction and a width direction. Moreover, an empirical value is determined that is indicative of an extension of the gate electrode in the length direction. Furthermore, the method includes completing the field effect transistor by: (a) forming a first spacer element adjacent to the gate electrode; (b) implanting ions into the substrate to form lightly doped regions adjacent to the gate electrode; (c) forming a second spacer element adjacent to the first spacer element; and (d) implanting ions into the substrate to form a source and a drain region. Thereby, at least one process parameter for controlling at least one of the process steps (a)-(d) is controlled on the basis of the empirical value.
In a further illustrative embodiment of the present invention, a method of controlling an electrical property of a field effect transistor during fabrication of the same comprises forming a gate electrode of the field effect transistor, wherein the gate electrode defines a width direction and a length direction. Furthermore, the method includes obtaining an empirical value indicative of a gate length of the gate electrode and forming a spacer element adjacent to the sidewall of the gate electrode while controlling at least one process parameter during the formation of the spacer element. Thereby, the controlling is performed such that a maximum extension of the spacer element in the length direction is increased when the empirical value indicates that the gate length is less than a predefined setting value and such that the maximum extension is decreased when the empirical value indicates that the gate length exceeds the predefined setting value.
According to a further illustrative embodiment of the present invention, a method of developing a run-to-run model for controlling an electrical property of a field effect transistor comprises determining a first plurality of experimental values, each being indicative of a gate length of the field effect transistor to be formed. Moreover, for each of the first experimental values, a second experimental value is determined that is indicative of at least one electrical property of the field effect transistor. Additionally, the method includes specifying at least one allowable setting value for the gate length of the field effect transistor on the basis of the first and second experimental values.
In a further illustrative embodiment of the present invention, a method of controlling the effective gate length of a field effect transistor comprises providing a substrate having formed thereon a gate electrode defining a length direction and a width direction. Moreover, an extension of the gate electrode in the length direction is determined by a measurement. Additionally, the method comprises forming doped regions adjacent to the gate electrode, wherein an implantation profile is controlled in correspondence to the extension of the gate electrode previously determined.
In a further embodiment, a system for controlling an electrical property of a field effect transistor during fabrication of the field effect transistor comprises a feed forward controller adapted to receive measurement results that indicate a gate length of a gate electrode formed on a substrate that has been processed, and to output at least one control signal to a process tool used for manufacturing the field effect transistor after the gate electrode has been formed. Furthermore, the system includes a communication line configured to transmit measurement signals to the feed forward controller and to provide said at least one control signal to the process tool.